1. Field of the Invention
The present invention relates to a semiconductor memory device capable of recovering defective bit and a system having the same semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device having built-in self-test function in which a test function is incorporated in a chip so as to reduce overhead of its chip area and simplify processing steps.
2. Description of the Background Art
With recently increased scale of LSI, system LSI containing a large capacity memory such as SRAM, DRAM and flash memory has appeared. Generally, these memory cells use stricter processing rules than other logic area for high integration and their critical area (area designed based on minimum processing rule) is enlarged. Therefore, a yield rate of the memory cell is lower than other logic portions.
To solve this problem, the memory that is incorporated in system as well as general purpose memory is provided with a defective memory recovery means such as a redundancy circuit and employs a method for increasing the yield rate of the system LSI.
FIG. 1 shows an example of configuration of memory redundancy circuit. Referring to FIG. 1, a proper memory array 100 is composed of m rows x n columns and a row decoder 101 selects a desired row (i-th row). As a result, all memory cells connected to the i-th row are activated. Each column is connected to n-bit bus line through a reading circuit 102 and a writing circuit 103. A content of the memory cell is accessed by the reading circuit 102 and writing circuit 103 of the memory cell connected to the selected i-th column.
In such a configuration, to enable recovery of the defective bit of, for example, 1 bit, a redundant bit column 104 is disposed in the vicinity of the proper memory array 100.
Usually, a reading circuit 102 and writing circuit 103 equivalent to the reading circuit and writing circuit of the proper memory array 100 are connected to this redundancy bit column 104 in redundant condition.
If there is a defective bit in the j-th row and k-th column, all memory cells of the k-th column in both the reading circuit and writing circuit are inhibited to use. Then, the memory cell column of the (k+1)-th column, reading circuit 102 and writing circuit 103 are connected to the k-th bit bus line. Next, a memory cell column of the (k+2)-th column, reading circuit and writing circuit are connected to the bus line of the (k+1)-th bit. That is, the connection to the bus line is shifted by 1 bit. A memory cell column of a redundant bit column 104, reading circuit and writing circuit are connected to the bus line of the n-th bit. This recovery method for redundancy is called shift redundancy. This shift redundancy is a very effective method for a memory having a large bus width like a memory incorporated in system LSI. As a result, a proper function of the memory is never lost even if a defective bit of 1 bit exists.
Therefore, even if there is found a defective bit, it can be recovered so that the yield rate is improved remarkably.
FIG. 2 shows a structure of a program circuit 105 (shown in FIG. 1) for achieving the aforementioned bit shift. In FIG. 2, this program circuit 105 is disposed at each bit column.
Usually, both inputs of logical product (AND) gate 106 are of high level, and the bit column and bus line of the proper memory array 100 are connected to each other corresponding to the same bit column by a multiplexer (MUX) 107.
If the redundancy of a memory cell of the k-th column is achieved, the fuse 108 composed of metallic wiring layer or polysilicon wiring layer corresponding to the k-th column is melted down with the use of laser beam or the like, so that one input of the AND gate 106 becomes low level. Then, the MUX 107 connects the (k+1)-th column of the proper memory array to the bus line of the k-th bit and the output of the AND gate of the k-th column is transmitted to all the AND gates 106 of the upper side. Then, the upper bit MUX after the k-th bit selects the upper bit column and connection is shifted from the k-th column including the defective bit to adjoining (k+1)-th column. Because this shift information is propagated to the program circuits 105 from the k-th bit to the n-th bit through the AND gate 106. Therefore, single defective bit can be repaired by melting of single fuse 108.
However, because the aforementioned redundancy recovery method using the fuse facilitates melting down of the fuse, first, additional processing step such as thinning of the protective film on the fuse is necessary for easy melt down. Second, because the fuse is melted down by laser beam, the fuse layout pattern cannot be decreased in size and further, any active element or wiring layer cannot be disposed in the fuse region. Thus, there is a problem that the overhead of area is increased.
FIG. 3 shows a flowchart of a test process for system LSI including a redundant circuit by BIST (built-inself-test). In this BIST, first, memory test is carried out on the wafer (step S10) and the fuse 108 of a column including the defective bit is melted down (step S11). The memory test is carried out again on the wafer in which connection is shifted (step S12) and die sort by function test is carried out (step S14). Memory test (step S15) in package and final test (step S16) are carried out.
As shown in FIG. 3, the redundancy recovery method using the fuse has such a problem that a post process for melting of the fuse and an additional memory test after the melting of the fuse are necessary. Further, if any defective bit is contained in the memory cell from the beginning, the logical circuit having no redundancy means cannot be tested sufficiently in the first memory test and therefore, additional test must be carried out after the redundancy processing. Therefore, there is another problem that the test cost is increased.
To solve such a problem, the BISR (built-in self-repair) method has been proposed, in which the defective bit is extracted using the aforementioned BIST method and then this defective bit information is memorized in a register so as to realize the melting of the fuse.
FIG. 4 shows an example of a structure of the self-test circuit of the memory using the BIST. Referring to FIG. 4, the BIST comprises an address pattern generator 111 for a test target memory 110, a data pattern generator 112, an expected value generator 113b and a comparator 113 for comparing an expected value attached to the bus of each bit with read out data. Then, the BIST realizes a function of memory tester in a LSI chip so as to determine whether the memory array is acceptable. In the aforementioned, the register is connected to an output of this comparator 113 and a result of determining whether or not the bit is acceptable is stored in this register. This register plays the same role as the aforementioned fuse, so that connection is shifted to adjoining memory cell column without using a memory cell column in which the defective cell exists.
FIG. 5 shows an example of the structure of the BISR. In this BISR circuit, data read out from the memory cell is compared with an expected value and a result of the comparison is stored in the register and bit shift is realized for recovery of the defective bit depending on the storage content. In FIG. 5, the readout data amplified by a sense amplifier (S/A) 114 is compared with the expected value in an exclusive NOR (EX-NOR) gate 115 and this comparison result is held by the register 116. If the comparison result does not coincide, xe2x80x9c0xe2x80x9d is held by the register 116 and this information is propagated to the upper bit side through the AND gates 117, 118. As a result, the shift to the upper bit is carried out by the MUX 119 as described above, so that the defective bit column is replaced with the redundant bit column.
However, this BISR method of holding information of the defective cell in the register 116 can only maintain the defect information temporarily, different from the melting down of the fuse. Therefore, even if the BISR employs the register, the BISR still needs to employ the fuse at the same time. As a result, regarding the above described problems, it comes only that the memory portion can determine whether or not other logical circuit is acceptable for a chip which may be recovered, before the processing step of meltdown of the fuse. Therefore, even if the BISR is employed, a problem that an additional processing step for introducing the fuse is added and an overhead of the chip area have not been solved.
FIG. 6 shows a flowchart of test procedure of the memory by the BISR. In the final die sort by the function test, first, memory test by the BIST is carried out (step S1a). If a defect is detected (YES in step S1b), if the defect may be recovered (YES at step S1c), the defective bit is replaced with redundant column (step S1d). Then, the function test is carried out (step S1e) and the defective bit is checked again (step S1f), so as to determine whether or not the object memory is acceptable. In the memory test using the BIST, the fuse melting-down step (step S2) and post-test test processing (step S16) are still necessary.
To eliminate the necessity of the fuse completely, it can be considered to hold defect information in the register by carrying out the aforementioned test by BISR each time when the system is started up. However, there is no guarantee that the environment at the time of system startup will not change from the environment at the actual system operation. For example, it can be considered that the temperature in the casing at the time of system startup is low and the temperature increases gradually when the system is operated. If the system is operated for a long time, it is affected by a change in temperature outside the casing. Further, the system power supply may be affected by a change in the ambient temperature, a change with time passage and other operating condition of the system. Therefore, a memory cell having a small operating margin and which manages to pass a test depending on condition at the time of system startup has a possibility that it may induce a fault with changes in voltage/temperature at the time of system operation. If this occurs, the system reliability is damaged remarkably.
Usually, in the shipment test on the LSI, margin test of the operating environment is carried out by changing the operating environment such as high temperature/low temperature, high voltage/low voltage and the like. Because redundancy is achieved by determining whether or not the memory cell is acceptable through these steps, any memory cell having no operating margin from the beginning has been already detected by screening upon shipment. Therefore, even if just the test by the BISR is carried out without melting down the fuse at the time of system startup, no practical performance is achieved.
As described above, in the first redundancy recovery method using the fuse in order to hold defect information, fuse occupied area increases so that the overhead of area also increases, thereby inducing a disadvantage that integration of the memory cell is hampered. Further, a fuse melt-down step and an additional test step after the fuse is melted down are required, so that a large number of time and labor are consumed by such an increase of the processing steps.
On the other hand, with the user of the second method, the defect information is held in a register by carrying out the aforementioned test by the BISR each time the system containing a memory that employs the conventional redundancy recovery method with the fuse is started up. Therefore, the necessity of the fuse is eliminated. In this method, however, there is a fear that the system environment changes between system startup and system operation. Thus, there occurs a following disadvantage that only if the test by BISR is carried out at the time of system startup, a change of the operating environment with a passage of time cannot be taken into account.
An object of the present invention is to provide a semiconductor memory device capable of simplifying a test process, while reducing an overhead of memory area and maintaining a practical-level accuracy of the memory circuit, by enabling redundancy of a defective bit without use of a fuse in the test of a memory circuit containing a nonvolatile memory, and a system incorporating the same semiconductor memory device.
Another object of the present invention is to provide a semiconductor memory device in which recovery of redundancy of the defective bit is enabled by a fuse formed out of a circuit formation region in the test of a memory circuit without any nonvolatile memory, and a system incorporating the same semiconductor memory device.
To achieve the above object, according to an aspect of the present invention, there is provided a semiconductor memory device for replacing a defective memory cell detected in a test with a redundant memory cell, comprising: a proper memory cell array; a redundant memory cell with which the defective memory cell in the proper memory cell array is to be replaced; a register for holding defect information of the defective memory cell detected in the proper memory cell array temporarily; a control circuit for replacing the defective memory cell with the redundant memory cell according to the defect information of the memory cell held in the register; a redundant program array which is an expansion of the same memory cell as the proper memory cell array while sharing a column with the proper memory cell array so as to store defect information in the same column as the defective memory cell; a writing circuit for writing defect information held in the register into the redundant program array; and a reading circuit for reading the defect information stored in the redundant program array into the register.
Preferably, the proper memory cell array is a nonvolatile memory.
Preferably, the control circuit is composed of a built-in self-repair circuit.
Preferably, the reading circuit reads the defect information stored in the redundant program array at the time of start-up.
According to another aspect of the present invention, there is provided a semiconductor memory device for replacing a defective memory cell detected in a test with a redundant memory cell, comprising: a volatile semiconductor memory, including, a volatile proper memory cell array; a first redundant memory cell with which the defective memory cell in the proper memory cell array is to be replaced; a first register for holding defect information of the defective memory cell in the proper memory cell array temporarily; and a first control circuit for replacing the defective memory cell with the redundant memory cell according to the defect information of the memory cell held in the first register, and a nonvolatile semiconductor memory, including, a nonvolatile proper memory cell array; a second register which is connected to the first register while a holding content is scanned and transferred mutually and defect information of defective volatile memory cell in the proper volatile memory cell array scanned and transferred from the first register is held temporarily; a redundant program array which is an expansion of the same memory cell as the nonvolatile proper memory cell array while sharing a column with the proper nonvolatile memory cell array so as to store the defect information of the defective volatile memory cell held in the second register; a writing circuit for writing the defect information held in the second register in the redundant program array; and a reading circuit for reading defect information stored in the redundant program array into the second register.
Preferably, a holding content of the first and second registers is inputted and outputted by scanning.
Preferably, the nonvolatile semiconductor memory further includes: a second redundant program array for storing defect information of the defective nonvolatile memory cell in the proper nonvolatile memory cell array.
Preferably, the nonvolatile semiconductor memory further includes, a nonvolatile redundant memory cell with which the defective nonvolatile memory cell is to be replaced; and a second control circuit for replacing the defective nonvolatile memory cell with the nonvolatile redundant memory cell according to the defect information held in the second register.
Preferably, the nonvolatile semiconductor memory further includes: a first program array which is an expansion of the same memory cell as the proper nonvolatile memory cell array while sharing a column with the proper nonvolatile memory cell array so as to store defect information which is held in the first register and then transferred to the second register by scanning; and a second program array which is an expansion of the same memory cell as the proper nonvolatile memory cell array while sharing a column with the proper nonvolatile memory cell array so as to store defect information of the nonvolatile memory cell held in the second register.
According to another aspect of the present invention, there is provided a semiconductor memory device for replacing a defective memory cell in a proper memory cell array with a redundant memory cell provided preliminarily based on defect information so as to recover the defective memory cell, comprising: a proper memory cell array; a fuse disposed in a pad formation region out of a circuit formation region for storing defect information of a defective memory cell; and a transfer unit for transferring the defect information of the defective memory cell stored in the fuse to a memory main body in the circuit formation region.
According to another aspect of the present invention, there is provided a built-in self-test semiconductor memory device for replacing a defective memory cell detected in a test with a redundant memory cell, comprising: a test unit for carrying out a test for determining whether or not a memory cell is acceptable each time when the device is started in order to determine whether or not the memory cell is acceptable; a register for holding defect information of a defective memory cell in a memory cell tested by the test unit temporarily; a redundant memory cell with which the defective memory cell it to be replaced;
a control circuit for replacing the defective memory cell with the redundant memory cell according to the defect information held in the register; and a control voltage source for generating a plurality of access voltages which are different mutually for accessing the memory cell and supplying generated each access voltage to the memory cell at the time of the test carried out by the test unit, wherein the test unit carries out the test of the memory cell based on a plurality of different access voltages supplied from the control voltage source to the memory cell and determines whether or not the memory cell is acceptable according to a result of the test.
The memory cell may be composed of static random access memory cell and the access voltage is an activation voltage for a word line of the memory cell.
The memory cell may be composed of dynamic random access memory cell and the access voltage is an activation voltage for a word line of the memory cell and a plate of capacitor constituting the memory cell.
The memory cell may be composed of nonvolatile memory cell and the access voltage is an activation voltage for a writing word line and a reading word line.
According to another aspect of the present invention, there is provided a system incorporating a semiconductor memory device for replacing a defective memory cell detected in a test with a redundant memory cell, comprising: a proper memory cell array; a redundant memory cell with which the defective memory cell in the proper memory cell array is to be replaced; a register for holding defect information of the defective memory cell detected in the proper memory cell array temporarily; a control circuit for replacing the defective memory cell with the redundant memory cell according to the defect information of the memory cell held in the register; a redundant program array which is an expansion of the same memory cell as the proper memory cell array while sharing a column with the proper memory cell array so as to store defect information in the same column as the defective memory cell; a writing circuit for writing defect information held in the register into the redundant program array; a reading circuit for reading the defect information stored in the redundant program array into the register; and a processing unit for carrying out a desired processing using the semiconductor memory device.
According to another aspect of the present invention, there is provided a system incorporating a semiconductor memory device for replacing a defective memory cell detected in a test with a redundant memory cell, comprising: a volatile semiconductor memory, including, a volatile proper memory cell array; a first redundant memory cell with which the defective memory cell in the proper memory cell array is to be replaced; a first register for holding defect information of the defective memory cell in the proper memory cell array temporarily; and a first control circuit for replacing the defective memory cell with the redundant memory cell according to the defect information of the memory cell held in the first register, and a nonvolatile semiconductor memory, including, a nonvolatile proper memory cell array; a second register which is connected to the first register while a holding content is scanned and transferred mutually and defect information of defective volatile memory cell in the proper volatile memory cell array scanned and transferred from the first register is held temporarily; a redundant program array which is an expansion of the same memory cell as the nonvolatile proper memory cell array while sharing a column with the proper nonvolatile memory cell array so as to store the defect information of the defective volatile memory cell held in the second register; a writing circuit for writing the defect information held in the second register in the redundant program array; and a reading circuit for reading defect information stored in the redundant program array into the second register, and a processing unit for carrying out a desired processing using the semiconductor memory device.
Other features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings.